1. Field of the Invention
The present invention relates generally to improvements in electron beam exposure for writing desired patterns on a semiconductor wafer, and more specifically to a method of implementing electron beam lithography using uniquely positioned alignment marks. Still more specifically, the present invention relates to a semiconductor wafer itself which is previously provided with the above mentioned alignment marks.
2. Description of Related Art
As the feature size of ICs (integrated circuits) continues to decrease, electron beam lithography has been found suitable for higher image resolution. Electron beam lithography (viz., electron beam exposure) has the advantage of being able to eliminate the need for reticles or masks each representing a circuit pattern to be formed. As is known, the electron beam exposure is able to directly write or draw patterns in accordance with circuit design data outputted from a CAD (computer aided design) system.
Unfortunately, high-quality electron beam systems are expensive. Further, due to the time-consuming sequential nature of the exposure method, production rates are low compared to the mask techniques of optical lithography. Thus, electron beam lithography is typically used to produce semiconductor devices, such as ASICs (application specific integrated circuits), custom ICs (integrated circuit), etc., each of which is of multi-sort but small-production quantities and which is required to be delivered within a limited time.
The sequence of IC fabrication consists of multiple processing steps that add, alter and remove thin layers. Each of these processing steps requires extremely strict alignment or registration. To this end, alignment marks are formed on a semiconductor wafer and are used as references for aligning at each processing step.
According to conventional optical lithography (photolithography), an alignment mark, which is to be used in a subsequent step, is formed in each chip region during the first exposing process via which cell segregation layers are formed. That is, the cell segregation layers can be formed in the range of alignment precision of a stepper itself. Accordingly, in the case of photolithography, there is no need to provide a processing step dedicated to forming the alignment marks.
On the other hand, in the case of electron beam lithography, the alignment is implemented by detecting electron beams reflected at an alignment mark. The alignment mark is formed so as to have a height sufficient to enable the detection of the mark in the manner disclosed. Therefore, in the case of electron beam lithography, it is necessary to provide a processing stage which is dedicated to forming alignment marks prior to the first actual IC fabrication process of forming cell separation layers.
One conventional technique in connection with the electron beam alignment marks will be described with reference to FIG. 1.
As shown in FIG. 1, a silicon semiconductor wafer 10 is provided with a plurality of alignment marks 12. These marks are respectively formed within corresponding chip regions 14 each of which is square or rectangular and indicated by a broken line. Each alignment mark is cross-shaped in this particular case. Throughout the instant disclosure, the term "chip region" implies a region on which electronic circuitry is to be formed. After all the processing steps on the wafer have ebeen completed, the wafer is cut into a plurality of chips (viz., diced) and packaged. The area or region between adjacent chip regions 14 is a dicing region or margin.
The chip regions 14 respectively carry the cross-shaped alignment marks 12 in the same positions thereof, each of which has been determined considering the size of the chip to be fabricated and the arrangement of the chip regions 14. In order to prepare such an alignment mark, a reticle is prepared taking the chip size into account. Thereafter, the mark 12 is formed via photolithographic techniques using step-repeat optical exposure of a stepper. The linear strip-like spaces, which are formed between the adjacent chip regions 14, are dicing regions or scribe lines along which the wafer is cut into individual chips.
There are two types of alignment techniques used for implementing electron beam exposure: one is die-by-die alignment carried out at each chip region and the other is global alignment for aligning the entire wafer surface. An EGA (enhanced global alignment) method disclosed in the Japanese Patent Application Tokkai-hei No. 8-181066 is classified as one kind of the global alignment. In order to implement the electron beam exposure using the global alignment, it is necessary to detect a plurality of alignment marks 12.
The chip size and the number of chip regions on one wafer are different with different ASICs and custom ICs. Therefore, the aforesaid conventional technique has encountered the problem that the chip size can not be determined until the circuit design is completely finished, which results in a long turnaround time. Especially, in the case where different reticles must be prepared with different chip sizes, the conventional technique suffers from the difficulty that the turnaround time become extremely long.